Gated SR Latch (D-Latch)

So we looked at the SR Latch.

But that required 2 data lines to store one bit of data. What would be more useful is if we could have one data line and one enable line. Where the enable allows us to write date to the latch and if enable is not active the latch will ignore the data line. The block diagram looks something like this.

As you can see the Active low section is the SR-Latch, and added before that is the Gate which is controlled by the E (Enable)

So when E is High and D is High the Q (Data) is High. And when E is released Q stays High, and then you can release D and Q will stay High until E is High again and D is High or Low which would result in Q being High or Low.

Also note that the D-Latch is now Active High.

The Schematic for the D-Latch gets a bit more complicated.

Now putting it on the breadboard gets even more complicated (But this also works).